The growing demand for high performance data storage and access in various consumer electronic and computing devices has driven the development of nonvolatile memory (NVM) technologies. Resistive random access memory (ReRAM) is one of alternative NVMs used because of its low operating voltage, high speed and scalability. ReRAM is employed in computers, mobile computing devices, memory cards, and the like. For more information regarding ReRAM, please see commonly assigned U.S. Pat. No. 6,867,996, hereby incorporated by reference in its entirety.
A ReRAM module is composed of a plurality of memory tiles. Each of the memory tiles further comprises an array of memory cells. The memory cells each represent a “bit” in memory. Each memory cell comprises, minimally, a transistor coupled to a resistive material, further coupled to a common source line voltage (CSL). The transistor is further coupled to a bit-line and a word-line. A bit is modified in the memory cell based on the direction bias across the memory cell. For example, the “set” operation sets a high resistance to a low resistance in the resistive material of the memory cell. A “reset” operation has the polarity of the direction bias reversed, setting a low resistance to a high resistance in the resistive material of the memory cell.
However, due to the small size of the memory tile in a ReRAM module and the large number of cells in each memory tile, the CSL tends to accumulate a large parasitic capacitance. The large parasitic capacitance can generate parasitic oscillations in the ReRAM module, increases the rise and fall times of digital pulse signals for selecting and modifying memory cells, and can cause other unwanted side effects in the circuit resulting in undesired and excessive power usage.
Therefore, there is a need in the art to prevent the unwanted side effects of the large parasitic capacitance in the CSL of ReRAM modules.